1. Field of the Invention
The present invention generally relates to an apparatus and method of depositing a conductive material over sub-micron apertures formed on a substrate.
2. Description of the Related Art
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. However, as the boundaries of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technologies have placed additional demands on the processing capabilities and consistent uniform control of the device formation process. The multilevel interconnects that lie at the heart of these technologies requires precise processing of complex features such as single or dual damascene structures and high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects and reliable connection of these features to other devices is very important to VLSI and ULSI success and to the continued effort to increase circuit density and device yield of individual substrates.
Semiconductor processing generally involves the deposition of material onto and removal (“etching”) of material from substrates. Typical deposition processes include chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating. Removal processes include chemical mechanical planarization (CMP) etching and others. During the processing and handling of substrates, the substrates undergo various structural and chemical changes. Illustrative changes include the thickness of layers disposed on the substrate, the material of layers formed on the substrate, surface morphology, changes in the device patterns, etc. These changes must be controlled in order to produce the desired electrical characteristics of the devices formed on the substrate. In the case of etching, for example, end-point detection methods are used to determine when the requisite amount of material has been removed from the substrate. More generally, successful processing requires ensuring the correct process recipe, controlling process excursions (e.g., gas flow, temperature, pressure, electromagnetic energy, duration, etc) and the like.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology, because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current carrying capacity, and a significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities required for the high levels of integration and increased device speed. Copper can be deposited by various techniques such as PVD, CVD and electroplating.
Typical device features utilizing copper or copper alloys are single damascene or dual damascene processes. In damascene processes, a feature is etched in a dielectric material and subsequently filled with copper. A barrier layer is deposited conformally on the surfaces of the features formed in the dielectric layer prior to deposition of the copper. Copper is then deposited over the barrier layer and the surrounding field. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, typically a slurry or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition, or slurry, to effect chemical activity and/or mechanical activity and consequential removal of material from the surface of the substrate.
After the surface of the substrate has been planarized the surface will generally comprise an array of exposed features and a “filed area” comprising some form dielectric material that electrically isolates the features from one another. The exposed features may contain such interconnecting metals as copper, aluminum or tungsten and barrier materials such as tantalum, tantalum nitride, titanium, titanium nitride, cobalt, ruthenium, molybdenum, etc.
Even though copper has been selected as one of the favorite interconnection materials it has a couple drawbacks, since it is difficult to etch, it has a tendency to form a stable oxide layer when exposed to the atmosphere, and can form various corrosion products when exposed to other aggressive semiconductor fabrication environments. The formation of the stable oxide layer can greatly affect the reliability of the connections. To resolve this problem, various methods have been employed to deposit a more inert metallic layer, or capping layer, over the interconnecting materials to reduce the oxidation of the surface or the subsequent attack of the exposed layers. The capping layer can be deposited by physical vapor deposition (PVD), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD) or electroless deposition processes. Since PVD, CVD, ALD and MBE will indiscriminately and not selectively deposit the capping layer material across the surface of the substrate, subsequent polishing or patterning and etching will be required to electrically isolate the exposed features. The added steps of polishing, pattering and etching adds great complexity to the device forming process. Therefore, electroless deposition processes are often preferred.
Although electroless deposition techniques have been widely used to deposit conductive metals over non-conductive printed circuit boards, electroless deposition techniques have not been extensively used for forming interconnects in VLSI and ULSI semiconductors. Electroless deposition involves an autocatalyzed chemical deposition process that does not require an applied current for the reaction to occur. Electroless deposition typically involves exposing a substrate to a solution by immersing the substrate in a bath or by spraying the solution over the substrate. Deposition of a conductive material in micron technology by electroless or electroplating techniques require a surface capable of electron transfer for nucleation of the conductive material to occur over that surface. Non-metal surfaces and oxidized surfaces are examples of surfaces which cannot participate in electron transfer. Barrier layers comprising titanium, titanium nitride, tantalum, and/or tantalum nitride are poor surfaces for nucleation of a subsequently deposited conductive material layer, since native oxides of these barrier layer materials are easily formed.
One issue that arises with the use of an electroless deposition process is the effect that surface contamination or oxidation has on the time it takes the electroless deposition process to begin or “initiate.” This time, often known as the “initiation time,” is strongly dependent on the ability of the catalytic layer fluid or deposition fluid to interact with the surface of the interconnect feature. Once the electroless reaction has initiated, the time to deposit a defined amount of material is predictable and will generally fall into a relatively repeatable range of deposition rates. However, since if there is no way to know when the process has initiated and the initiation time varies from substrate to substrate or from one area of a substrate to another it is hard to know when the desired thickness of material has been deposited across the surface of the substrate. To compensate for this type of process variation, engineers will often use a worst case processing time to assure that a desired amount of material is deposited across the surface of the substrate or from one substrate to another. Use of a worst case process time causes the throughput of the deposition chamber to suffer and is wasteful of the often expensive electroless deposition solutions. Also, variations in thickness of the deposited film across the surface of the substrate and/or the variations substrate-to-substrate will cause variations in the processing speed (e.g., propagation delay) of the formed devices. The variation in speed of the formed devices, created by the variation in resistance (i.e., varying thickness) can have a large affect on device yield.
Therefore, there is a need for an improved apparatus and method for monitoring and detecting the endpoint of an electroless deposition process.